1. Field of the Invention
The present invention relates to semiconductor processing, and more particularly to a system and method for employing feature characteristics, such as, liner thickness as an indicator of thermal stress during temperature cycles in metal structures.
2. Description of the Related Art
Reliability under thermal cycle conditions is one of the main concerns when integrating Back End of Line (BEOL) structures with low dielectric constant dielectrics. The cause of thermal cycle fails is typically the mismatch in the coefficients of thermal expansion (CTE) between the metallization and the surrounding insulator. For example, the CTE of copper (Cu) is approximately 16 ppm/° C. while that of SiLK™ (trademark of Dow Chemical) is approximately 60 ppm/° C. As a result, the Cu metallization is strained during thermal cycle testing, which can lead to crack formation in Cu vias and eventual failure. While the thermal cycle performance of a given process can be evaluated by stressing specifically designed test structures, such as stacked via chains, this can only be done on a limited sampling of parts and only on complete builds of the structure.
It would be highly desirable to have a method and apparatus for determining the thermal cycle performance provided by a manufacturing process before completing manufacturing of the device.